About the job

This is a technical role in semiconductor and ASIC development, where the Verification Engineer will work on digital ASIC design and verification, including SystemVerilog, UVM, and Formal Verification. The role involves collaborating with senior principal engineers, mentoring and guiding peers, translating design requirements into RTL, deriving functional requirements for verification, and working with scripting languages and REST APIs such as Perl, Python, or TCL. Candidates will contribute to high-volume data center and enterprise products, using leading-edge EDA tools and methodologies, and may work with international teams. The position also includes opportunities for career development through role-specific training and direct guidance from an industry-renowned Senior Director. Visa sponsorship and relocation support are available, along with competitive salary, bonus, hybrid work, pension, private medical insurance, and other employee benefits.