About the job

Flux Computing is seeking a highly skilled Senior/Staff Analog Design Engineer specializing in CMOS phase-locked loops (PLLs) and clock-distribution networks to design and implement ultra-low-jitter clocking subsystems for Optical Tensor Processing Units (OTPUs). The role involves architecting and verifying multi-GHz fractional-N PLLs, developing precise clock-distribution networks for over 100 optical-compute channels, co-optimizing with packaging, board, and power-delivery teams, creating behavioral and transistor-level models for system-level simulation, performing post-layout extraction and Monte-Carlo analysis, and leading silicon bring-up and validation including on-wafer phase-noise and jitter measurements. Candidates must have deep expertise in analog/RF design, signal integrity, loop dynamics, electromagnetic crosstalk, and precision clock generation, with 7+ years of industry experience, a Bachelor’s in Electrical Engineering (Master’s/PhD preferred), and strong problem-solving and collaboration skills. Frequent travel between Austin and London offices may be required. The company offers competitive compensation, stock options, high-end workstations, BUPA healthcare, relocation support, and visa sponsorship for eligible candidates, making this an excellent opportunity for those passionate about advancing AI hardware in a high-energy, fast-paced environment.