About the job

The Senior IC Layout Engineer role at IC Resources in Reading offers a unique opportunity to lead custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high-speed SerDes beyond 28Gb/s and/or memory IO in advanced semiconductor technology nodes. Candidates will have the chance to guide chip layout activities, ensuring career growth and seeing their work in final products. Required experience includes custom analog layout for high-speed circuits such as amplifiers, oscillators, PLLs/DLLs, biasing, buffers, regulators, filters, and data converters, using layout techniques to manage parasitics, power grids, matching, and ESD. Familiarity with modern semiconductor process technologies (28nm, 14/16nm, 7nm) and EDA tools like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, EM, IR drop, and ESD is expected. The role offers a competitive salary, benefits including pension and private medical, and provides visa sponsorship and relocation support where needed, making it an excellent opportunity for skilled analog IC layout engineers.