About the job

IC Resources is seeking a Senior IC Layout Engineer for a leading semiconductor client based in Reading, Berkshire. This role involves taking ownership of the custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high-speed SerDes and memory IO in advanced semiconductor nodes, offering significant opportunities to lead chip layout activities and see your work in the final product. The ideal candidate will have strong experience in high-speed analog IC layout, including layout of amplifiers, oscillators, phase-locked loops, delay-locked loops, biasing circuits, buffers, regulators, filters, and data converters, with a focus on matching constraints, minimization of parasitics, power grids, and ESD requirements. Experience with modern semiconductor process technologies such as 28nm, 14/16nm, or 7nm, and EDA tools for design and verification including Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitic extraction, EM/IR drop, and ESD analysis is essential. The company offers a competitive salary, benefits including pension and private medical, as well as visa sponsorship and relocation assistance where required, making this an excellent opportunity for experienced Analog IC Layout Engineers seeking career growth in a high-growth, internationally recognized semiconductor company.