About the job

The Lead Verification Engineer will take ownership of verification strategies for complex WiFi SoC ASIC designs, develop and implement UVM-based testbenches and environments in SystemVerilog, collaborate with cross-functional design and architecture teams to ensure first-time success, mentor and guide junior verification engineers, and continuously improve verification processes, methodologies, and best practices. The role requires a Bachelor’s or Master’s degree in Electrical or Computer Engineering or a related discipline, proven experience in ASIC verification, ideally with complex SoC designs, proficiency in SystemVerilog and UVM methodology, strong leadership and communication skills, and WiFi or wireless SoC experience is highly desirable. Day-to-day responsibilities include leading verification efforts, defining methodologies, building and maintaining UVM-based environments, performing simulations and debugging issues, developing verification plans and documentation, and participating in design and code reviews. The position offers a base salary of £90,000–£100,000, RSU allocation, annual bonus scheme, hybrid work (3 days onsite in Bristol), and visa sponsorship/relocation support for candidates outside the UK.