About the job

The Formal Verification Engineer will apply formal methods to verify the correctness of complex digital designs, working closely with design, simulation, and functional verification teams to ensure product reliability, safety, and compliance. Responsibilities include developing and executing formal verification plans for digital blocks and systems, identifying key properties and invariants, writing formal specifications using SystemVerilog Assertions (SVA), PSL, or other languages, analyzing results including counterexamples and traces, integrating formal methods into overall verification strategies, documenting methodologies and best practices, and using EDA tools such as JasperGold, Questa Formal, or OneSpin. Candidates should hold a Bachelor’s or Master’s in Electrical, Computer Engineering, Computer Science, or related field, with solid understanding of digital design, RTL design (Verilog/SystemVerilog, VHDL), experience with formal verification tools, and strong knowledge of logic, Boolean algebra, and formal specification languages. Familiarity with bus protocols and microarchitecture concepts is desirable. Visa sponsorship and relocation support are available for candidates from overseas.