About the job

The Formal Verification Engineer role at Elite People Partners Ltd. offers an exciting opportunity to work with a semiconductor client on cutting-edge SoC and ASIC development projects. The successful candidates will collaborate with industry experts in various aspects of design and verification, working on state-of-the-art technologies. The role involves mentoring from senior engineers, learning different parts of the design and verification cycle, and contributing to high-volume data centre and enterprise products. This position provides a chance to work within a multi-disciplinary team, gain experience with leading-edge EDA tools, and expand skills in areas such as RTL Design, Formal Verification, and DevOps. Ideal candidates will have 5 to 15+ years of experience in the industry, with skills in Systemverilog, UVM test benches, scripting languages (Perl, Python, TCL), and formal verification tools like Jasper Gold or VC_Formal. The job also offers visa sponsorship, relocation support, and hybrid working.