About the job

A highly skilled and detail-oriented Formal Verification Engineer is sought to join an established and experienced verification group based in the historic city of Oxford, England. This role offers an exciting opportunity to apply formal methods to ensure the correctness, reliability, and safety of complex digital designs. The successful candidate will work closely with design, simulation, and functional verification teams to develop and execute formal verification plans, identify key properties for analysis, write formal specifications using SystemVerilog Assertions (SVA), PSL, or similar languages, and analyze results including counterexamples and traces to resolve design issues. The role requires a solid understanding of digital design principles, including RTL design using Verilog, SystemVerilog, or VHDL, and familiarity with formal verification tools such as JasperGold, Questa Formal, or OneSpin. Candidates should also possess strong knowledge of logic, Boolean algebra, and be comfortable with microarchitecture concepts and common bus protocols. Applicants must hold a Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline. This position is open to both UK and non-UK nationals, with full visa sponsorship and relocation support available for successful international candidates. Offering a salary in the range of £80,000 to £110,000 depending on experience, plus a performance bonus, this is a compelling opportunity for a talented engineer to advance their career in a technically rich, supportive, and globally connected environment.