About the job

Elite People Partners Ltd is seeking a highly skilled Design Verification Engineer to join a semiconductor client’s cutting-edge SoC team in Oxfordshire, England. The role involves performing functional or formal verification for ASIC development, mentoring and guiding engineers, collaborating with senior principal engineers, and contributing expert knowledge across the entire design and verification cycle. Candidates will work with leading-edge EDA tools and industry-standard languages and methodologies such as SystemVerilog, UVM, and formal verification platforms, as well as scripting languages like Python, Perl, and TCL. The position includes working on high-volume data centre and enterprise products used by industry-leading companies, and collaborating with internationally distributed teams. Ideal candidates will have 5–10+ years of digital ASIC design and verification experience, expertise in translating design requirements into RTL, deriving functional requirements for verification, building SystemVerilog UVM testbenches, and strong team communication skills. Preferred skills include experience with formal verification tools like Jasper Gold or VC_Formal, knowledge of C/C++, and familiarity with storage interfaces such as SAS, PCIe, NVMe, or SATA. The role offers a competitive salary of £70K–£90K per year depending on experience, a 10–20% performance bonus, 25 days holiday plus bank holidays, hybrid working (three days on-site), matched pension contributions, life assurance, income protection, private medical insurance, employee well-being support, training and development, visa sponsorship, and relocation support if required, with a fast three-stage interview process including video calls and an on-site visit.